#ifndef H_RCGD_SWITCH_H
#define H_RCGD_SWITCH_H


#ifndef SIOCGMIIPHY
#define SIOCGMIIPHY 0x8947	/* Read from current PHY */
#define SIOCGMIIREG 0x8948 	/* Read any PHY register */
#define SIOCSMIIREG 0x8949 	/* Write any PHY register */
#define SIOCGPARAMS (SIOCDEVPRIVATE+3) 	/* Read operational parameters */
#define SIOCSPARAMS (SIOCDEVPRIVATE+4) 	/* Set operational parameters */
#endif

#define PHY_BMCR            0x0000
#define PHY_BMSR            0x0001
#define PHY_IDR1            0x0002
#define PHY_IDR2            0x0003
#define PHY_ANAR            0x0004
#define PHY_ANLPAR          0x0005
#define PHY_ANER            0x0006
#define PHY_ANNPTR          0x0007
#define PHY_PHYSTS          0x0010
#define PHY_MICR            0x0011
#define PHY_MISR            0x0012
#define PHY_PAGESEL         0x0013
#define PHY_FCSCR           0x0014
#define PHY_RECR            0x0015
#define PHY_PCSR            0x0016
#define PHY_RBR             0x0017
#define PHY_LEDCR           0x0018
#define PHY_PHYCTRL         0x0019
#define PHY_10BTSCR         0x001A
#define PHY_CDCTRL1         0x001B
#define PHY_EDCR            0x001D

/* DP83640 specific */
// Phy Register Indexes - Common Across Device Types
#define DP83640_PHY_BMCR            0x0000
#define DP83640_PHY_BMSR            0x0001
#define DP83640_PHY_IDR1            0x0002
#define DP83640_PHY_IDR2            0x0003
#define DP83640_PHY_ANAR            0x0004
#define DP83640_PHY_ANLPAR          0x0005
#define DP83640_PHY_ANER            0x0006
#define DP83640_PHY_ANNPTR          0x0007
#define DP83640_PHY_PHYSTS          0x0010
#define DP83640_PHY_MICR            0x0011
#define DP83640_PHY_MISR            0x0012
#define DP83640_PHY_PAGESEL         0x0013
#define DP83640_PHY_FCSCR           0x0014
#define DP83640_PHY_RECR            0x0015
#define DP83640_PHY_PCSR            0x0016
#define DP83640_PHY_RBR             0x0017
#define DP83640_PHY_LEDCR           0x0018
#define DP83640_PHY_PHYCTRL         0x0019
#define DP83640_PHY_10BTSCR         0x001A
#define DP83640_PHY_CDCTRL1         0x001B
#define DP83640_PHY_EDCR            0x001D

// DP83848 Specific Register Indexes
#define DP83640_PHY_AFECR           0x001E
#define DP83640_PHY_AFEAR           0x001F

// DP83849 / DP83640 Specific Register Indexes
// Note: Bits [6:5] specify the register page (00-pg0, 01-pg1, 10-pg2, 11-pg3)
#define DP83640_PHY_PG0_PHYCR2      0x001C
#define DP83640_PHY_PG1_PMDCNFG     0x0034
#define DP83640_PHY_PG1_TMR1        0x0035
#define DP83640_PHY_PG1_TMR2        0x0036
#define DP83640_PHY_PG1_DSP_CTRL1   0x0037
#define DP83640_PHY_PG1_DSP_CTRL2   0x0038
#define DP83640_PHY_PG1_TRL_CTRL    0x0039
#define DP83640_PHY_PG1_DEQ_CTRL    0x003A
#define DP83640_PHY_PG1_ANEG_TST    0x003B
#define DP83640_PHY_PG1_EXTCFG      0x003C
#define DP83640_PHY_PG1_TST_CTRL    0x003D
#define DP83640_PHY_PG1_SD_CNFG     0x003E
#define DP83640_PHY_PG1_TSTDAT      0x003F
#define DP83640_PHY_PG2_LEN100_DET  0x0054
#define DP83640_PHY_PG2_FREQ100     0x0055
#define DP83640_PHY_PG2_TDR_CTRL    0x0056
#define DP83640_PHY_PG2_TDR_WIN     0x0057
#define DP83640_PHY_PG2_TDR_PEAK    0x0058
#define DP83640_PHY_PG2_TDR_THR     0x0059
#define DP83640_PHY_PG2_VAR_CTRL    0x005A
#define DP83640_PHY_PG2_VAR_DATA    0x005B
#define DP83640_PHY_PG2_LQMR        0x005D
#define DP83640_PHY_PG2_LQDR        0x005E

// DP83640 Specific Register Indexes
// Note: Bits [7:5] specify the register page (000-pg0, 001-pg1, 010-pg2, 011-pg3, etc.)
#define DP83640_PHY_PG2_LQMR2       0x005F
#define DP83640_PHY_PG3_CGCR        0x0074
#define DP83640_PHY_PG3_PTPTR       0x0075
#define DP83640_PHY_PG3_CDCR1       0x0077
#define DP83640_PHY_PG3_CDCR2       0x0078
#define DP83640_PHY_PG3_FCO1CR      0x0079
#define DP83640_PHY_PG3_FCO2CR      0x007A
#define DP83640_PHY_PG3_ADCCR1      0x007B
#define DP83640_PHY_PG3_ADCCR2      0x007C
#define DP83640_PHY_PG3_BGREGCR     0x007D
#define DP83640_PHY_PG3_CGMCR       0x007E
#define DP83640_PHY_PG3_PGMCR       0x007F
#define DP83640_PHY_PG4_PTP_CTL     0x0094
#define DP83640_PHY_PG4_PTP_TDR     0x0095
#define DP83640_PHY_PG4_PTP_STS     0x0096
#define DP83640_PHY_PG4_PTP_TSTS    0x0097
#define DP83640_PHY_PG4_PTP_RATEL   0x0098
#define DP83640_PHY_PG4_PTP_RATEH   0x0099
#define DP83640_PHY_PG4_PTP_RDCKSUM 0x009A
#define DP83640_PHY_PG4_PTP_WRCKSUM 0x009B
#define DP83640_PHY_PG4_PTP_TXTS    0x009C
#define DP83640_PHY_PG4_PTP_RXTS    0x009D
#define DP83640_PHY_PG4_PTP_ESTS    0x009E
#define DP83640_PHY_PG4_PTP_EDATA   0x009F
#define DP83640_PHY_PG5_PTP_TRIG    0x00B4
#define DP83640_PHY_PG5_PTP_EVNT    0x00B5
#define DP83640_PHY_PG5_PTP_TXCFG0  0x00B6
#define DP83640_PHY_PG5_PTP_TXCFG1  0x00B7
#define DP83640_PHY_PG5_PSF_CFG0    0x00B8
#define DP83640_PHY_PG5_PTP_RXCFG0  0x00B9
#define DP83640_PHY_PG5_PTP_RXCFG1  0x00BA
#define DP83640_PHY_PG5_PTP_RXCFG2  0x00BB
#define DP83640_PHY_PG5_PTP_RXCFG3  0x00BC
#define DP83640_PHY_PG5_PTP_RXCFG4  0x00BD
#define DP83640_PHY_PG5_PTP_TRDL    0x00BE
#define DP83640_PHY_PG5_PTP_TRDH    0x00BF
#define DP83640_PHY_PG6_PTP_COC     0x00D4
#define DP83640_PHY_PG6_PSF_CFG1    0x00D5
#define DP83640_PHY_PG6_PSF_CFG2    0x00D6
#define DP83640_PHY_PG6_PSF_CFG3    0x00D7
#define DP83640_PHY_PG6_PSF_CFG4    0x00D8
#define DP83640_PHY_PG6_PTP_SFDCFG  0x00D9
#define DP83640_PHY_PG6_PTP_INTCTL  0x00DA
#define DP83640_PHY_PG6_PTP_CLKSRC  0x00DB
#define DP83640_PHY_PG6_PTP_ETR     0x00DC
#define DP83640_PHY_PG6_PTP_OFF     0x00DD
#define DP83640_PHY_PG6_PTP_GPIOMON 0x00DE
#define DP83640_PHY_PG6_PTP_RXHASH  0x00DF

#define EMAC_NCR_OFFSET				0
#define EMAC_NCFGR_OFFSET			1
#define EMAC_NSR_OFFSET				2
#define EMAC_TSR_OFFSET				5
#define EMAC_RBQP_OFFSET			6
#define EMAC_TBQP_OFFSET			7
#define EMAC_RSR_OFFSET				8
#define EMAC_ISR_OFFSET				9
#define EMAC_IER_OFFSET				10
#define EMAC_IDR_OFFSET				11
#define EMAC_IMR_OFFSET				12
#define EMAC_MAN_OFFSET				13
#define EMAC_PTR_OFFSET             14
#define EMAC_PFR_OFFSET             15
#define EMAC_FTO_OFFSET             16
#define EMAC_SCF_OFFSET             17
#define EMAC_MCF_OFFSET             18
#define EMAC_FRO_OFFSET             19
#define EMAC_FCSE_OFFSET            20
#define EMAC_ALE_OFFSET             21
#define EMAC_DTF_OFFSET             22
#define EMAC_LCOL_OFFSET            23
#define EMAC_ECOL_OFFSET            24
#define EMAC_TUND_OFFSET            25
#define EMAC_CSE_OFFSET             26
#define EMAC_RRE_OFFSET             27
#define EMAC_ROV_OFFSET             28
#define EMAC_RSE_OFFSET             29
#define EMAC_ELE_OFFSET             30
#define EMAC_RJA_OFFSET             31
#define EMAC_USF_OFFSET             32
#define EMAC_STE_OFFSET             33
#define EMAC_RLE_OFFSET             34
#define EMAC_TPF_OFFSET             35
#define EMAC_HRB_OFFSET             36
#define EMAC_HRT_OFFSET             37
#define EMAC_SA1L_OFFSET            38
#define EMAC_SA1H_OFFSET            39
#define EMAC_SA2L_OFFSET            40
#define EMAC_SA2H_OFFSET            41
#define EMAC_SA3L_OFFSET            42
#define EMAC_SA3H_OFFSET            43
#define EMAC_SA4L_OFFSET            44
#define EMAC_SA4H_OFFSET            45
#define EMAC_TID_OFFSET             46
#define EMAC_TPQ_OFFSET             47
#define EMAC_USRIO_OFFSET           48
#define EMAC_WOL_OFFSET             49
#define EMAC_REV_OFFSET             63
	

/* bool define */
#ifndef TRUE
#define TRUE  1
#endif

#ifndef FALSE
#define FALSE  0
#endif

#ifndef true
#define true  1
#endif

#ifndef false
#define false 0
#endif


void InitDual ();
void CheckDual ();



extern void ClearFail ();
extern void ReadTraceValue ();
extern void StartPLL ();
extern void CheckSynchTest ();
extern void AdjustSynch ();
extern void ReadSynch ();
extern void UnconditionalSigOn ();
extern void UnconditionalSigOff ();
extern void AdjustEventEnable ();
extern void SigOnWithReadyOff ();
extern void SigOffWithReadyOn ();
extern void SetMyStatus ();
extern void SetHWSwitchingCondition ();
extern void lsiReadModuleID ();
extern void Lsi00sec ();
extern void Lsi01sec ();
extern void Lsi05sec ();
extern void Lsi10sec ();
extern void Lsi15sec ();
extern void Lsi20sec ();
extern void Lsi30sec ();
extern void Lsi300sec ();
extern void LsiTest ();



extern int bLsiMonitorEnable;
extern int iLsiDebugVariable;




#define ADC_CHANNEL_0	0x0000
#define ADC_CHANNEL_1	0x0001
#define ADC_CHANNEL_2	0x0002
#define ADC_CHANNEL_3	0x0003
#define ADC_CHANNEL_4	0x0004
#define ADC_CHANNEL_5	0x0005
#define ADC_CHANNEL_6	0x0006
#define ADC_CHANNEL_7	0x0007


#define ADC_NEW_DETAIL_CHANNEL50NS	ADC_CHANNEL_0
#define ADC_U_DETAIL_CHANNEL500NS	ADC_CHANNEL_4
#define ADC_U_DETAIL_CHANNEL50NS	ADC_CHANNEL_5
#define ADC_DETAIL_CHANNEL			ADC_CHANNEL_1

#define ADC_VCXO_EFC_CHANNEL		ADC_CHANNEL_3
#define ADC_PLUS_5V_CHANNEL			ADC_CHANNEL_5
#define ADC_PLUS_VCC_CHANNEL		ADC_CHANNEL_2
#define ADC_MINUS_VEE_CHANNEL		ADC_CHANNEL_5


#define ADC_MAX_VALUE 1024

#define VREF			(3.3)
#define VEE_VOLTAGE		(-12.0)
#define VCC_VOLTAGE		(12.0)


//---------------------------------------
/*
            8.2K
+5V : -------- *5V = 2.0297V
        12K + 8.2K


              3K
+12V : -------- *12V =  2V
         15K + 3K


             10K                    8.2K
-12V : -------- *12V + -------- *(-12V) =  1.1869V
         10K + 8.2K            10K + 8.2K


*/
//---------------------------------------

#define PLUS_5V_MULTIPLY_VALUE	(5/2.0297)
#define VCC_MULTIPLY_VALUE		(6)
#define VEE_MULTIPLY_VALUE		(-12/1.1869)






extern unsigned short usADCValue, ReferenceADC, usADCVcxo, usADCDetail,usADCU_Detail500ns,usADCU_Detail50ns;


extern float fPlus5V, fPlusVcc, fMinusVee, fVCXOEfc;

extern void MonitorADCValue (int usChannel);

#define MonitorADC(); 					
#define MonitorPlus5V(); 				//kang MonitorADCValue(ADC_PLUS_5V_CHANNEL);
#define MonitorPlusVcc(); 				//kang MonitorADCValue(ADC_PLUS_VCC_CHANNEL);
#define MonitorMinusVee(); 				//kang MonitorADCValue(ADC_MINUS_VEE_CHANNEL);
#define MonitorVCXOEfc(); 				
#define	MonitorDetailCounter();			
#define	MonitorU_DetailCounter500ns();	
#define	MonitorU_DetailCounter50ns();	

#define	MonitorNewDetailCounter();		MonitorADCValue(ADC_NEW_DETAIL_CHANNEL50NS);

//#endif


#define FLOATPOINT_ERR_RESET 1



extern void SetRTCAll (time_);
extern void GetRTCAll (time_ *);

extern char odetic_debug;
extern char tod_debug;
extern char time_debug;
extern unsigned int fp_err_flag;



extern char start_unlock;
extern char eb_tdebug;
extern char slope_debug;


extern float g_detail;
extern int detail_cnt;


extern int SelMonitorStatusDebug;

extern char debug_calc;
extern char no_system_fail;
extern char temp_sensor_debug;
extern int debug_send_local;
extern int config_debug;
extern int log_debug;
extern int dual_fail_debug;
extern int dual_clear_debug;
extern int wdt_debug;
extern int temp_debug;

extern int dual_rx_debug;
extern int dual_tx_debug;
extern int debug_out_udp;
#endif

